This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...

The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. The LDS SATA HOST STR4GX IP is compliant with ...

Both character and FIFO modes are supported. The 16550D High Speed UART IP core is an RTL design in Verilog and VHDL that implements an UART on an ASIC, or FPGA. The core includes RTL code, test ...